The present invention relates to a semiconductor device and a method of producing the same.
For achieving a decrease in power consumption of transistors constituting a logic circuit (also called a peripheral circuit) and an increase in the speed thereof, it has come to be standard practice to apply a salicide (self-aligned silicide) technology and a dual gate (also called dual work function gate or surface channel type CMOSFET) technology. Further, a semiconductor device having logic circuits and dynamic random access memories (DRAM) mounted together has come to be generally used.
The above salicide technology refers to the technology of forming a silicide layer, in source/drain regions and a top surface of a gate electrode, in a self-aligned manner. In this technology, specifically, the gate electrode composed of polysilicon is formed on a semiconductor substrate, then, the source/drain regions are formed in the semiconductor substrate, then, a metal layer is formed on the entire surface, and heat treatment is carried out to allow atoms constituting the metal layer and atoms (specifically Si) constituting the semiconductor substrate and the gate electrode to react, whereby a silicide layer is formed, followed by the removal of the unreacted metal layer.
The above dual gate technology refers to the technology of forming a gate electrode for an n-channel type MOSFET from a polysilicon layer containing an n-type impurity and forming a gate electrode for a p-channel type MOSFET from a polysilicon layer containing a p-type impurity to form a surface channel in each MOSFET.
The semiconductor device is becoming finer in size, and when a contact plug is formed on a source/drain region of a semiconductor device, generally, there is therefore employed technology of forming the contact plug in a self-aligned manner. Such a technology is called xe2x80x9cself-align-contact (SAC) technologyxe2x80x9d. For applying the SAC technology, the gate electrode is required to have a two-layered structure formed of a polysilicon layer and an offset layer such as a silicon nitride (SiN) layer. For securing the distance between the gate electrode and the contact plug, further, it is required to form gate sidewalls composed of silicon nitride (SiN) on the side walls of the gate electrode.
However, it is said that the compatibility of the fast logic circuit production process including the salicide technology and the dual gate technology and the general DRAM production process is not so well for the following reasons.
[{circle around (1)} DRAM Memory Cell Characteristics]
For securing excellent characteristics of DRAM memory cells, it is preferred not to form a silicide layer on source/drain regions of a transistor constituting a memory element of the DRAM (to be sometimes referred to as xe2x80x9cDRAM-constituting transistorxe2x80x9d for the convenience hereinafter) for the following reason. That is, due to a leak current caused by a junction which takes place between the source/drain region on a node side and the silicide layer, the data-retention characteristic is deteriorated. Generally, 256 memory elements are connected to one bit line in DRAM of 0.25 xcexcm generation, and 512 memory elements are connected to one bit line in DRAM of 0.18 xcexcm generation. Due to an increase in a leak current as a total sum of leak currents caused by junctions between the source/drain regions on a bit line side and the silicide layers, a margin of a low-voltage driving lowers or decreases because of a decrease in the amplitude of a signal flowing in the bit line, and the data-retaining characteristic (for example, refresh characteristic) deteriorates. In the transistor constituting the logic circuit, it is required to improve the source/drain regions in performance by decreasing the resistance thereof, and for this purpose, it is required to form the silicide layers in the source/drain regions.
[{circle around (2)} SAC Technology of DRAM-constituting Transistor]
When the SAC technology is applied to DRAM-constituting transistors, and if a space between the gate electrodes of the transistors is fully filled with a silicon nitride layer, it is inevitable to increase the thickness of the offset layer for making an opening portion in the above silicon nitride layer while reliably securing a process margin. However, when the thickness of the offset layer is increased, a step height difference caused by the gate electrode increases, and disadvantages are liable to occur in steps to follow. Specifically, for example, a margin in a lithography step is liable to decrease, and filling of an insulating interlayer is liable to be defective.
Moreover, when silicon nitride having a relative dielectric constant approximately twice as large as that of silicon oxide is used as a gate sidewall, a fringe capacitance which is a capacitance between the edge portion of the gate electrode and the source/drain region increases, and the fast operation characteristic of the transistor constituting the logic circuit may be affected in some cases.
[{circle around (3)} Space Between Gate Electrodes of DRAM-constituting Transistors]
The distance between the gate electrodes of DRAM-constituting transistors is smaller than the distance between the gate electrodes of transistors constituting the logic circuit. In some cell design, therefore, the width (thickness) of the gate sidewall is determined by optimizing the capability of the transistors constituting the logic circuit, and when such a gate sidewall is formed on the side wall of the gate electrode, a silicon nitride film constituting the gate sidewall may fill a space between the gate electrodes of the DRAM-constituting transistors. Further, if a silicon nitride film is formed as an etching stop layer when a contact plug is formed on the source/drain region of the transistor constituting the logic circuit, the possibility of the silicon nitride film fully filling the space between the gate electrodes of the DRAM-constituting transistors comes to be higher. If the silicon nitride film fully fills the space between the gate electrodes of the DRAM-constituting transistors, it is very difficult to form a contact plug on the source/drain region of the DRAM-constituting transistor according to the SAC technology.
[{circle around (4)} Offset Layer]
When the gate electrode is formed to have the two-layer structure of the polysilicon layer and the offset layer, no silicide layer can be formed on the top surface of the gate electrode due to the presence of the offset layer. Further, when the dual gate technology is applied to the transistor constituting the logic circuit, the conventional process requires the steps of introducing an n-type impurity and a p-type impurity into the polysilicon layer, respectively, then, forming the offset layer, and then, patterning the offset layer and the polysilicon layer. Since, however, the polysilicon layer containing an n-type impurity and the polysilicon layer containing a p-type impurity have different etching rates, it is difficult to simultaneously form the gate electrode having a desired form for an n-channel type MOSFET and the gate electrode having a desired form for a p-channel type MOSFET. Further, the gate insulating layer keeps on decreasing in thickness, so that a semiconductor substrate may be damaged when etching is carried out for forming the gate electrode.
When the offset layer is made from silicon nitride, the step of forming the contact plug on the gate electrode, an extending portion of the gate electrode or a word line inevitably differs from the step of forming the contact plug on the source/drain region, so that additional steps of exposure and etching are required.
It is therefore a first object of the present invention to provide a semiconductor device which can overcome the problems described in the above [{circle around (1)} DRAM memory cell characteristics].
It is a second object of the present invention to provide a semiconductor device and a method of producing the same, which can overcome the problems described in [{circle around (2)} SAC technology of DRAM-constituting transistor].
Further, it is a third object of the present invention to provide a method of producing a semiconductor device, which serves to establish consistency between the fast logic circuit production process including the salicide technology and the dual gate technology and the general DRAM production process and which can overcome the problems described in the above [{circle around (1)} DRAM memory cell characteristics] and [{circle around (3)} Space between gate electrodes of DRAM-constituting transistors].
It is further a fourth object of the present invention to provide a method of producing a semiconductor device, which can overcome the problems described in the above [{circle around (4)} Offset layer] in addition to the above third object.
It is further a fifth object of the present invention to provide a method of producing a semiconductor device, which can overcome the problems described in the above [{circle around (2)} SAC technology of DRAM-constituting transistor] in addition to the above third object.
The first object of the present invention is achieved by a semiconductor device according to a first aspect of the present invention, comprising a plurality of first transistors formed in a first region of a semiconductor substrate and a plurality of second transistors formed in a second region of the semiconductor substrate,
wherein each of the first and second transistors has a gate electrode, a channel-forming region and source/drain regions,
the gate electrodes constituting the first and second transistors are formed of a polysilicon layer containing an impurity and a silicide layer formed thereon,
a silicide layer is formed in the source/drain regions constituting the first transistor, and
no silicide layer is formed in the source/drain regions constituting the second transistor.
In the semiconductor device according to the first aspect of the present invention, or in a method of producing a semiconductor device according to the first or second aspect of the present invention explained later, a logic circuit is constituted of the first transistors, and a dynamic random access memory (DRAM) is constituted of the second transistor.
In the semiconductor device according to the first aspect of the present invention, for achieving the second object of the present invention, preferably, each of the first and second transistors has (a) an insulating material layer which is composed of a first insulating material and covers at least part of each of side walls of each gate electrode and (b) a cap layer which is composed of a second insulating material and covers a top surface of each gate electrode and a top portion of the insulating material layer. The entire side walls of each gate electrode may be covered with the insulating material layer, or lower portions of the side walls of each gate electrode may be covered with the insulating material layer. In the latter case, more specifically, the lower portions of the side walls of the polysilicon layer may be covered, the entire side walls of the polysilicon layer may be covered, the entire side walls of the polysilicon layer and lower portions of side walls of the silicide layer may be covered, or the entire side walls of the polysilicon layer and the entire side walls of the silicide layer may be covered, with the insulating material layer. Preferably, a relative dielectric constant of the first insulating material is lower than that of the second insulating material, or an etching rate of the cap layer is lower than that of the insulating material layer. The first insulating material includes silicon oxide (SiO2: relative dielectric constant 3.7-3.9), and the second insulating material includes silicon nitride (SiN: relative dielectric constant 6-7). The cap layer has an eaves-like structure extending from the gate electrode, and there is formed a structure in which the insulating material layer is present below the eaves-like portion of the cap layer which portion extends from the gate electrode, so that the cap layer can be decreased in thickness and there can be overcome the problem that a step height difference caused by the gate electrode increases which causes disadvantages in a step to follow. That is, there can be overcome the problems described in the above [{circle around (2)} SAC technology of DRAM-constituting transistor]. Further, when the relative dielectric constant of the first insulating material is lower than that of the second insulating material, an increase in the fringe capacitance can be suppressed, and particularly, an influence on the fast operation characteristic of the transistors constituting a logic circuit can be minimized.
The above second object of the present invention is achieved by a semiconductor device, according to a second aspect of the present invention, said semiconductor device having;
(a) a gate electrode composed of an electric conductive material,
(b) an insulating material layer which is composed of a first insulating material and covers at least part of each of side walls of the gate electrode, and
(c) a cap layer which is composed of a second insulating material and covers a top surface of the gate electrode and a top portion of the insulating material layer.
The entire side walls of the gate electrode may be covered, or lower portions of the side walls of the gate electrode may be covered, with the insulating material layer. In the latter case, remaining upper portions of the side walls of the gate electrode are covered with the cap layer.
In the semiconductor device according to the second aspect of the present invention, preferably, a relative dielectric constant of the first insulating material is lower than that of the second insulating material, or an etching rate of the cap layer is lower than that of an insulating material layer. The first insulating material includes silicon oxide (SiO2), and the second insulating material includes silicon nitride (SiN). Preferably, the gate electrode is formed of a polysilicon layer containing an impurity and a silicide layer formed thereon. In this case, lower portions of the side walls of the polysilicon layer may be covered, the entire side walls of the polysilicon layer may be covered, the entire side walls of the polysilicon layer and lower portions of the side walls of the silicide layer may be covered, or the entire side walls of the polysilicon layer and the entire side walls of the silicide layer may be covered, with the insulating material layer.
The above third and fourth objects of the present invention are achieved by a method of producing a semiconductor device according to the first aspect of the present invention, said semiconductor device comprising a plurality of first transistors formed in a first region of a semiconductor substrate and a plurality of second transistors formed in a second region of the semiconductor substrate,
said method comprising the steps of;
(A) forming a gate insulating layer on the surface of the semiconductor substrate and then forming gate electrodes composed of a polysilicon for forming the first transistors and the second transistors, and then, forming source/drain regions constituting the second transistors in the semiconductor substrate,
(B) filling a space between the gate electrodes constituting the adjacent second transistors with an insulating material layer, and exposing a region of the semiconductor substrate in which region source/drain regions constituting the first transistors are to be formed, the top surface of the gate electrode constituting the first transistors and the top surface of the gate electrode constituting of the second transistors,
(C) forming source/drain regions in the region of the semiconductor substrate in which region the source/drain regions constituting the first transistors are to be formed, and
(D) forming a silicide layer in the source/drain regions constituting the first transistors, on the top surface of the gate electrode constituting the first transistors and on the top surface of the gate electrode constituting the second transistors, to obtain the gate electrodes formed of the polysilicon layer and the silicide layer formed thereon.
In the method of producing a semiconductor device according to the first aspect of the present invention, preferably, the insulating material layer is formed of a first insulating material layer and a second insulating material layer, and the above step (B) includes the steps of forming the first insulating material layer on the entire surface, then, forming the second insulating material layer on the first insulating material layer such that the space between the gate electrodes constituting the adjacent second transistors is filled with the second insulating material layer, and then removing the first insulating material layer on a region where the first transistors is to be formed and the first insulating material layer on the top surface of the gate electrode constituting the second transistors.
In this case, desirably, the above step (B) includes the steps of forming the first insulating material layer on the entire surface, then, forming the second insulating material layer on the first insulating material layer such that the space between the gate electrodes constituting the adjacent second transistors is filled with the second insulating material layer, then, forming a third insulating material layer on the entire surface, removing the third insulating material layer and the first insulating material layer on the top surface of the gate electrode constituting the second transistor, and selectively removing the third insulating material layer and the first insulating material layer on a region where the first transistors is to be formed, to retain a gate sidewall formed of the third insulating material layer and the first insulating material layer on each of the side walls of the gate electrode constituting the first transistor.
In the method of producing a semiconductor device according to the first aspect of the present invention, preferably, in the above step (C), when the source/drain regions are formed in a region of the semiconductor substrate in which region the source/drain regions constituting the first transistors are to be formed, the same impurity as that introduced into said source/drain regions is introduced into the gate electrode constituting the first transistor, and an impurity having the same conductivity type as that of an impurity introduced into the source/drain regions constituting the second transistors is introduced into the gate electrode constituting the second transistor.
In the method of producing a semiconductor device according to the first aspect of the present invention, desirably, the first insulating material layer is composed of silicon nitride (SiN), and the second insulating material layer is composed of a silicon-containing material. The term xe2x80x9csilicon-containing materialxe2x80x9d not only refers to silicon oxide (SiO2) but also refers to any one of SOG (Spin On Glass), PSG, BPSG, BSG, AsAG, PbSG, SbSG, NSG, LTO (low temperature oxide, lower temperature CVD-SiO2), a low-dielectric insulating material having a relative dielectric constant of 3.5 or less (for example, polyaryl ether, cycloperfluorocarbon polymer or benzocyclobutene), an organic polymer material such as polyimide, or stacking of these materials.
In the method of producing a semiconductor device according to the first aspect of the present invention, preferably, the above step (D) is further followed by the step (E) of consecutively forming an etching-stop layer and an insulating interlayer on the entire surface, forming an opening portion which penetrates through the insulating interlayer, the etching-stop layer and the insulating material layer and reaches the source/drain region constituting the second transistor, and filling the opening portion with an electric conductive material to form a contact plug. When the insulating material layer is formed of the first insulating material layer and the second insulating material layer, the opening portion is formed in the first insulating material layer and the second insulating material layer. An etching rate of the etching-stop layer is required to be lower than an etching rate of the insulating material layer. For example, when the insulating material layer is composed of silicon oxide (that is, when the second insulating material layer is composed of silicon oxide), desirably, the etching-stop layer is composed of silicon nitride.
The above third object of the present invention is achieved by a method of producing a semiconductor device according to the second aspect of the present invention, said semiconductor device comprising a plurality of first transistors formed in a first region of a semiconductor substrate and a plurality of second transistors formed in a second region of the semiconductor substrate,
said method comprising the steps of;
(A) forming a gate insulating layer on the surface of the semiconductor substrate and then forming gate electrodes composed of a polysilicon for forming the first transistors and the second transistors, and then, forming source/drain regions constituting the second transistors in the semiconductor substrate,
(B) covering the source/drain regions constituting the second transistors with a first insulating material layer, and exposing a region of the semiconductor substrate in which region source/drain regions constituting the first transistors are to be formed,
(C) forming source/drain regions in a region of the semiconductor substrate in which region the source/drain regions constituting the first transistors are to be formed, and then, forming a silicide layer in said source/drain regions,
(D) filling a space between the gate electrodes constituting the adjacent first transistors with a second insulating material layer, and a space between the gate electrodes constituting the adjacent second transistors with the second insulating material layer, and exposing the top surface of the gate electrode constituting the first transistors and the top surface of the gate electrode constituting the second transistor, and
(E) forming a silicide layer on the top surface of the gate electrode constituting the first transistors and the top surface of the gate electrode constituting the second transistor, to obtain the gate electrodes formed of the polysilicon layer and the silicide layer formed thereon.
In the method of producing a semiconductor device according to the second aspect of the present invention, preferably, the first and second insulating material layers are composed of silicon oxide (SiO2).
In the method of producing a semiconductor device according to the second aspect of the present invention, further for achieving the above fifth object, preferably,
the above step (A) includes the steps of forming the gate insulating layer on the surface of the semiconductor substrate for forming the first transistors and the second transistor, then, consecutively forming a polysilicon layer containing no impurity and an offset layer on the entire surface, then, patterning the offset layer and the polysilicon layer to form the gate electrodes having a two-layered structure of the polysilicon layer and the offset layer, and then, forming the source/drain regions constituting the second transistors in the semiconductor substrate,
the above step (B) includes the steps of covering the gate electrode and the source/drain regions constituting the second transistors with the first insulating material layer, simultaneously covering side walls of the gate electrode constituting the first transistors with the first insulating material layer, and exposing a region of the semiconductor substrate in which region the source/drain regions constituting the first transistors are to be formed,
the above steps (D) and (E) have an intervenient step of removing the offset layer and upper portions of the first insulating material layer on the side walls of the gate electrode constituting the first transistors and upper portions of the first insulating material layer on the side walls of the gate electrode constituting the second transistor, and
the above step (E) is followed by the steps of forming a first cap layer on the silicide layer formed on the gate electrode constituting the first transistors and on the top portions of the first insulating material layer on the side walls of the gate electrode constituting the first transistor, and forming a second cap layer on the silicide layer formed on the gate electrode constituting the second transistors and the top portions of the first insulating material layer on the side walls of the gate electrode constituting the second transistor.
In this case, desirably, an etching rate of the cap layer is lower than an etching rate of the first insulating material layer, or a relative dielectric constant of the material constituting the first insulating material layer is lower than a relative dielectric constant of a material constituting the cap layer. The material constituting the first and second insulating material layers includes silicon oxide (SiO2), and the material constituting the first and second cap layers includes silicon nitride (SiN). In the method of producing a semiconductor device according to the second aspect of the present invention, for achieving the above fourth object of the present invention, preferably, the above steps (D) and (E) have intervenient steps of removing the offset layer, then, introducing an impurity having the same conductivity type as that of an impurity introduced into the source/drain regions into the exposed polysilicon layer constituting the gate electrodes, and then, removing the upper portions of the first insulating material layer on the side walls of the gate electrode constituting the first transistors and the upper portions of the first insulating material layer on the side walls of the gate electrode constituting the second transistor. Otherwise, the steps (D) and (E) preferably have intervenient steps of removing the offset layer and the upper portions of the first insulating material layer on the side walls of the gate electrode constituting the first transistors and the upper portions of the first insulating material layer on the side walls of the gate electrode constituting the second transistor, and then, introducing an impurity having the same conductivity type as that of an impurity introduced into the source/drain regions into the polysilicon layer constituting the exposed gate electrodes.
In the method of producing a semiconductor device according to the second aspect of the present invention, further for achieving the above fifth object, preferably,
the above step (A) includes the steps of forming the gate insulating layer on the surface of the semiconductor substrate for forming the first transistors and the second transistor, then, consecutively forming a polysilicon layer containing no impurity and an offset layer on the entire surface, patterning the offset layer and the polysilicon layer to form the gate electrodes having a two-layered structure of the polysilicon layer and the offset layer, and then, forming the source/drain regions constituting the second transistors in the semiconductor substrate,
the above step (B) includes the steps of covering the gate electrode and the source/drain regions constituting the second transistors with the first insulating material layer, simultaneously covering the side walls of the gate electrode constituting the first transistors with the first insulating material layer, and exposing a region of the semiconductor substrate in which region the source/drain regions constituting the first transistors are to be formed,
the above steps (D) and (E) have an intervenient step of removing the offset layer, and
the above step (E) is followed by the steps of removing the upper portions of the first insulating material layer on the side walls of the gate electrode constituting the first transistors and the upper portions of the first insulating material layer on the side walls of the gate electrode constituting the second transistor, and then, forming a first cap layer on the silicide layer formed on the gate electrode constituting the first transistors and on the top portions of the first insulating material layer on the side walls of the gate electrode constituting the first transistor, and forming a second cap layer on the silicide layer formed on the gate electrode constituting the second transistors and on the top portions of the first insulating material layer on the side walls of the gate electrode constituting the second transistor.
In the above case, preferably, an etching rate of the cap layer is lower than an etching rate of the first insulating material layer, or a relative dielectric constant of a material constituting the first insulating material layer is lower than a relative dielectric constant of a material constituting the first and second cap layers. The material constituting the first and second insulating material layers includes silicon oxide (SiO2), and the material constituting the first and second cap layers includes silicon nitride (SiN). Further, for achieving the above fourth object of the present invention, preferably, the above steps (D) and (E) have intervenient steps of removing the offset layer, and then, introducing an impurity having the same conductivity type as that of an impurity introduced into the source/drain regions into the polysilicon layer constituting the exposed gate electrodes.
Further, in the method of producing a semiconductor device according to the second aspect of the present invention, preferably, the above step (E) is followed by the step (F) of forming an insulating interlayer on the entire surface, forming an opening portion which penetrate through the insulating interlayer and the second and first insulating material layers and reaches the source/drain region constituting the second transistor, and filling the opening portion with an electric conductive material to form a contact plug.
The above second object of the present invention is achieved by a method of producing a semiconductor device according to a third aspect of the present invention, said method comprising the steps of;
(A) forming a gate insulating layer on the surface of a semiconductor substrate, consecutively forming a polysilicon layer and an offset layer on the entire surface, and then, patterning the offset layer and the polysilicon layer to form a gate electrode having a two-layered structure of the polysilicon layer and the offset layer,
(B) covering side walls of the gate electrode with a first insulating material layer composed of a first insulating material and forming source/drain regions in the semiconductor substrate,
(C) filling a space between the adjacent gate electrodes with a second insulating material layer and exposing the top surface of the offset layer,
(D) removing the offset layer and simultaneously removing upper portions of the first insulating material layer covering the side walls of the gate electrode, and
(E) forming a cap layer on the top surface of the gate electrode and on the top portions of the first insulating material layer covering the side walls of the gate electrode.
In the step (B), the source/drain regions may be formed in the semiconductor substrate after the side walls of the gate electrode is covered with the first insulating material layer composed of the first insulating material, or the side walls of the gate electrode may be covered with the first insulating material layer composed of the first insulating material after the source/drain regions are formed in the semiconductor substrate.
In the method of producing a semiconductor device according to the third aspect of the present invention, preferably, in the above step (D), the offset layer is removed, then, a silicide layer is formed on the top surface of the polysilicon layer constituting the exposed gate electrode, and then, the upper portions of the first insulating material layer covering the side walls of the gate electrode are removed. In this case, further for achieving the above fourth object of the present invention, preferably, in the above step (D), the offset layer is removed, then, an impurity is introduced into the polysilicon layer constituting the exposed gate electrode, then, a silicide layer is formed on the top surface of the polysilicon layer, and then, the upper portions of the first insulating material layer covering the side walls of the gate electrode are removed.
Otherwise, in the method of producing a semiconductor device according to the third aspect of the present invention, preferably, in the above step (D), the offset layer and the upper portions of the first insulating material layer covering the side walls of the gate electrode are removed, and then, a silicide layer is formed on the top surface of the polysilicon layer constituting the exposed gate electrode. In this case, further for achieving the fourth object of the present invention, preferably, in the step (D), the offset layer is removed, an impurity is introduced into the polysilicon layer constituting the exposed gate electrode, the upper portions of the first insulating material layer covering the side walls of the gate electrode are removed, and then, a silicide layer is formed on the top surface of said polysilicon layer. Otherwise, preferably, in the step (D), the offset layer and the upper portions of the first insulating material layer covering the side walls of the gate electrode are removed, an impurity is introduced into the polysilicon layer constituting the exposed gate electrode, and then, a silicide layer is formed on the top surface of the polysilicon layer.
Otherwise, in the method of producing a semiconductor device according to the third aspect of the present invention, desirably, the above step (E) is followed by the step (F) of forming an insulating interlayer on the entire surface, forming an opening portion which penetrates through the insulating interlayer and the second insulating material layer and reaches the source/drain region, and then, filling the opening portion with an electrically conductive material to form a contact plug.
In this case, when the opening portion is formed by selectively etching the insulating interlayer and the second insulating material layer, preferably, the first insulating material layer below the cap layer is protected with the cap layer and is therefore not etched. When the first insulating material layer is present between the source/drain region and the second insulating material layer, there is formed an opening portion which penetrates through the insulating interlayer, the second insulating material layer and the first insulating material layer and reaches the source/drain region.
In the method of producing a semiconductor device according to the third aspect of the present invention, desirably, an etching rate of the cap layer is lower than an etching rate of the first insulating material layer, or a relative dielectric constant of the first insulating material is lower than a relative dielectric constant of the second insulating material. The first insulating material includes silicon oxide (SiO2), and the second insulating material includes silicon nitride (SiN).
In the semiconductor device or the method of producing a semiconductor device of the present invention, the semiconductor substrate includes a silicon semiconductor substrate, a substrate prepared by epitaxially growing a silicon crystal or a Sixe2x80x94Ge mixed crystal on a spinel, a substrate prepared by epitaxially growing a silicon crystal or a Sixe2x80x94Ge mixed crystal on a sapphire, and a substrate prepared by melting and recrystallizing polycrystal silicon on an insulating film. The silicon semiconductor substrate includes an n-type silicon semiconductor substrate which is doped with an n-type impurity and a p-type silicon semiconductor substrate which is doped with a p-type impurity.
Further, an SOI (Semiconductor On Insulator) substrate may be used as a semiconductor substrate. The method of producing the SOI substrate includes;
(1) a substrate-bonding method in which a semiconductor substrate and a supporting substrate are bonded to each other through an insulation layer and the semiconductor substrate is ground and polished from its back surface, to obtain a support formed of the supporting substrate, the insulating layer and a semi-conductive layer formed of the ground and polished semiconductor substrate,
(2) a smart-cut method in which an insulation layer is formed on a semiconductor substrate, then, the semiconductor substrate is ion-implanted with hydrogen ion to form a peel-off layer inside the semiconductor substrate, then, the semiconductor substrate and a supporting substrate are bonded to each other through the insulation layer, the resultant stack is heat-treated to peel (cleave) the semiconductor substrate from the peel-off layer, and, the remaining semiconductor substrate is ground and polished from its back surface, to obtain a support formed of the supporting substrate, the insulation layer and a semi-conductive layer formed of the ground and polished semiconductor substrate,
(3) a SIMOX (Separation by IMplanted OXygen) method in which oxygen ion is ion-implanted into a semiconductor substrate, then, the semiconductor substrate is heat-treated to form an insulation layer inside the semiconductor substrate, whereby a support formed of part of the semiconductor substrate is formed below the insulation layer and a semi-conductive layer formed of part of the semiconductor substrate is formed on the insulation layer,
(4) a method in which a single crystal semi-conductive layer is formed on an insulation layer formed on a semiconductor substrate corresponding to a support, in a gaseous phase or solid phase, to obtain a support formed of the semiconductor substrate, the insulation layer and a semi-conductive layer formed of the single crystal semi-conductive layer, and
(5) a method in which the surface of a semiconductor substrate is partially rendered porous by anodization, to form an insulation layer, whereby there are obtained a support formed of part of the semiconductor substrate below the insulation layer and a semi-conductive layer formed of part of the semiconductor substrate on the insulating layer. A semiconductor device is formed in the semi-conductive layer.
When the SOI substrate is used, a device-isolation region can be formed by any one of the following methods.
(a) A so-called LOCOS method in which a pad oxide film and a silicon nitride film are formed on the semi-conductive layer and the silicon nitride film and the pad oxide film are patterned, to form a mask for forming a device-isolation region, and the semi-conductive layer is thermally oxidized with using the mask to form a device-isolation region.
(b) A so-called STI (shallow trench isolation) method in which the semi-conductive layer is patterned to form a trench in the semi-conductive layer, and the trench is filled with an insulation material.
(c) A method of a combination of the substrate bonding method and the STI method, in which, when a substrate is prepared according the above method (1) or (2), a trench is first formed in a semiconductor substrate and filled with an insulation layer, then, an interlayer film (for example, an SiO2 film or a film having a stacked structure formed of an SiO2 film and a polysilicon film) is formed on the entire surface, the thus-prepared semiconductor substrate and a supporting substrate are bonded through the interlayer film, and the semiconductor substrate is ground and polished from its back surface, to obtain a support formed of the supporting substrate, the insulation layer and a semi-conductive layer formed of the semiconductor substrate.
(d) A method of forming a Mesa type device-isolation region, in which the semi-conductive layer on the insulation layer is removed to expose the insulating layer, whereby a device-isolation region is formed.
The silicide layer can be formed by the salicide technology in which a metal layer is formed on the entire surface, heat treatment is carried out to react atoms constituting the metal layer with atoms (specifically, Si) constituting the semiconductor substrate and/or the gate electrode, whereby a silicide layer is formed, and then unreacted metal layer is removed. The above metal layer can be composed, for example, of any one of cobalt (Co), nickel (Ni), platinum (Pt), titanium (Ti), Ta (tantalum), Mo (molybdenum), tungsten (W) and palladium (Pd).
In the semiconductor device according to the first aspect of the present invention, no silicide layer is formed in the source/drain regions constituting the second transistor, so that the problems described in the above [{circle around (1)} DRAM memory cell characteristics] can be overcome.
In the semiconductor device or the method of producing a semiconductor device according to the second aspect of the present invention, the cap layer has an eaves-like structure extending from the gate electrode, and the insulating material layer or the first insulating material layer is structurally present below the eaves-like portion of the cap layer which portion is extending from the gate electrode, so that the cap layer can be decreased in thickness and that there can be prevented the occurrence of the problem that a height level difference caused by the gate electrode increases and causes disadvantages in steps to follow. That is, the problems described in the above [{circle around (2)} SAC technology of DRAM-constituting transistor] can be overcome. Further, when the relative dielectric constant of the first insulating material is lower than the relative dielectric constant of the second insulating material, an increase in the fringe capacitance can be suppressed, and particularly, an influence on the fast operation characteristic of transistors constituting a logic circuit can be minimized.
In the method of producing a semiconductor device according to the first or second aspect of the present invention, the space between the gate electrodes constituting the adjacent second transistors is filled with the insulating material layer, so that no silicide layer is formed in the source/drain regions of the second transistor. As a result, the problems described in the [{circle around (1)} DRAM memory cell characteristics] can be overcome. Further, the space between the gate electrodes constituting the adjacent second transistors is filled with the insulating material layer, so that the problems described in the [{circle around (3)} Space between gate electrodes of DRAM-constituting transistors] can be overcome.
In the method of producing a semiconductor device according to the first aspect of the present invention, when the source/drain regions are formed in a region of the semiconductor substrate in which region source/drain regions constituting the first transistor are to be formed in the step (C) after the top surface of the gate electrode constituting the first transistor and the top surface of the gate electrode constituting the second transistors are exposed in the step (B), an impurity can be also introduced into these gate electrodes, so that the gate electrodes composed of a polysilicon containing no impurity can be formed in the step (A). Therefore, the problems described in the [{circle around (4)} Offset layer] can be overcome.